A semiconductor device includes a multilayer wiring structure. In order to form the multilayer wiring structure in a semiconductor device manufacturing procedure, a photolithography process of forming a resist pattern as a mask pattern for forming a wiring, is performed a plurality of times on a semiconductor wafer as a substrate (hereinafter, referred to as a “wafer”). Between respective photolithography processes, an exposure treatment is performed such that shots are performed in the same region of the wafer. As the wiring of the semiconductor device is miniaturized, it is requested that the accuracy of positional alignment between a region where a shot is performed in a previous photolithography process and a region where a shot is performed in a subsequent photolithography process, namely, the accuracy of overlay (superposition), is increased.
However, the wafer is mounted on a stage installed in an exposure device, and is sucked toward a surface of the stage by suction ports formed in the stage. An exposure shot is performed in the state where a position of the wafer is fixed on the stage. In this way, the wafer is subjected to an exposure treatment. However, there may be a case where a wafer conveyed to an exposure device is not flat and has distorted portions. If such a wafer is mounted on the stage, an exposure shot may be performed on the wafer which is sucked to the stage while being distorted. In such a case, the exposure shot is performed in a region that deviates away from a region where the shot is to be normally performed. This causes a limit in enhancing the accuracy of the overlay. In the related art, there is known a technique for detecting an error related to an overlay using a scatterometer, and controlling an operation of a scanner for performing exposure based on the detected error. However, this technique does not take into consideration the problem encountered when mounting the distorted wafer on the stage. Thus, this technique is not capable of solving the aforementioned problem.